A conventional output circuit used in a semiconductor integrated circuit device, for example, includes a signal input terminal, an enable signal terminal, an inverter, a 2-input NAND circuit, a 2-input NOR circuit, a PMOS transistor, an NMOS transistor, a power supply terminal supplied with a 3 V power supply potential, a ground terminal supplied with a ground potential, and an output terminal.
The signal input terminal is connected to one input terminal of each of the 2-input NAND circuit and the 2-input NOR circuit. The enable signal input terminal is connected to the other input terminal of the 2-input NAND circuit and the signal input terminal of the inverter circuit. The output terminal of the inverter circuit is connected to the other input terminal of the 2-input NOR circuit. The output terminal of the 2-input NAND circuit is connected to the gate electrode of the PMOS transistor, while the output terminal of the 2-input NOR circuit is connected to the gate electrode of the NMOS transistor. The PMOS transistor is connected between the power supply terminal (3 V) and the output terminal. The N-well in the substrate of the PMOS transistor is connected to the 3 V power supply terminal. The NMOS transistor is connected between the ground terminal and the output terminal, while the substrate of NMOS transistor (P-well) is connected to the ground terminal.
The operation of this circuit will now be described. First of all, when an `L` level signal (0 V) is inputted to the enable signal input terminal as an input signal, the output of the 2-input NAND circuit becomes an `H` level and the output of the 2-input NOR circuit becomes an `L` level. Accordingly, the PMOS transistor and the NMOS transistor are turned off. As a result, the output terminal is in a floating state totally unrelated to an input signal to the signal input terminal.
Next, when an `H` level signal is input to the enable signal input terminal as an input signal, if an `L` level signal is input to the signal input terminal the PMOS transistor is turned off and the NMOS transistor is turned on. As a result, the output terminal outputs an `L` level signal. On the other hand, if an `H` level signal is input to the signal input terminal, the PMOS transistor is turned on and the NMOS transistor is turned off. As a result, the output terminal outputs an `H` level signal.
However, in the conventional output circuit, when the output terminal is connected to an external element having a power supply voltage higher than 3 V, for example a bus etc. supplying signals of 5 V, there are circumstances in which the 5 V voltage can be applied to the output terminal while the output terminal is in the floating state. If a 5 V voltage is applied to the output terminal, the drain (P active) of the PMOS transistor becomes 5 V. Because the substrate (N-well) of this PMOS transistor is connected to the 3 V power supply terminal, the diode across the drain (P active) and the substrate (N-well) is forward biased, and so current flows in this diode across the drain and the substrate. This means that if a voltage of 5 V is applied to the output terminal due to the influence of the bus etc. having a 5 V signal supplied to it, there is a possibility of leakage current of a number of mA flowing in the path from the bus supplied with a 5 V signal, to the output terminal, to the drain of the PMOS transistor, to the substrate of the PMOS transistor, to power supply terminal of the output circuit.